Diferență între revizuiri ale paginii „Digital Systems Design - Project”
De la WikiLabs
Jump to navigationJump to search| Linia 10: | Linia 10: | ||
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor] | # [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor] | ||
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)] | # [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)] | ||
| − | # | + | # [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)] |
== Resources == | == Resources == | ||
Versiunea de la data 20 decembrie 2016 14:18
Design Specifications
- Simple RISC ISA v.2.3
- Pipeline implementation of the Simple RISC Processor v.1.0
- Superscalar implementation of the Simple RISC Processor v1.0
Assignments
- Sequential processor golden model
- Step by step design of the pipelined Simple RISC Processor
- Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)
- Step by step design of the superscalar Simple RISC Processor - B (Register renaming)
Resources
- Introduction to Verilog
- Vivado Design Suite Evaluation and WebPACK (Vivado HL WebPACK is free)
