DIC Lab Work 4

Notions and Knowledge Required

• Boolean logic and numbering systems
• Verilog Syntax Verilog_EN
• Using the Altera Quartus II Synthesis Program
• List of pins for DE1 board, List of pins for DE1-SoC board
• Sequential Circuits, Counter
• Pulse generator with variable duty cycle

Example

Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable fill factor signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.

Exercise

Build a circuit that instantiates 8 variable duty cycle (fill factor) signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:

• LEDG0 intensity, denoted I _LEDG0 is determined by SW7-SW0
• The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
  1. I _LEDG0 < I _LEDG1 < I _LEDG2 < I _LEDG3 < I _LEDG4 < I _LEDG5 < I _LEDG6 < I _LEDG7
  2. I _LEDG0 > I _LEDG1 < I _LEDG2 < I _LEDG3 < I _LEDG4 < I _LEDG5 < I _LEDG6 < I _LEDG7
  3. I _LEDG0 > I _LEDG1 > I _LEDG2 < I _LEDG3 < I _LEDG4 < I _LEDG5 < I _LEDG6 < I _LEDG7
  4. I _LEDG0 > I _LEDG1 > I _LEDG2 > I _LEDG3 < I _LEDG4 < I _LEDG5 < I _LEDG6 < I _LEDG7
  5. I _LEDG0 > I _LEDG1 > I _LEDG2 > I _LEDG3 > I _LEDG4 < I _LEDG5 < I _LEDG6 < I _LEDG7
  6. I _LEDG0 > I _LEDG1 > I _LEDG2 > I _LEDG3 > I _LEDG4 > I _LEDG5 < I _LEDG6 < I _LEDG7
  7. I _LEDG0 > I _LEDG1 > I _LEDG2 > I _LEDG3 > I _LEDG4 > I _LEDG5 > I _LEDG6 < I _LEDG7
  8. I _LEDG0 > I _LEDG1 > I _LEDG2 > I _LEDG3 > I _LEDG4 > I _LEDG5 > I _LEDG6 > I _LEDG7

Bonus Exercise

Build a circuit that then turns off a led gradually, using a variable fill factor generator.