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(Nu s-au afișat 6 versiuni intermediare efectuate de același utilizator)
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# [http://wiki.dcae.pub.ro/images/a/a2/DSD_Project_RISC1_MicroArch_v1_0.pdf Pipeline implementation of the Simple RISC Processor v.1.0]
 
# [http://wiki.dcae.pub.ro/images/a/a2/DSD_Project_RISC1_MicroArch_v1_0.pdf Pipeline implementation of the Simple RISC Processor v.1.0]
 
# [http://wiki.dcae.pub.ro/images/0/07/DSD_Project_RISC4_MicroArch_v1_0.pdf Superscalar implementation of the Simple RISC Processor v1.0]
 
# [http://wiki.dcae.pub.ro/images/0/07/DSD_Project_RISC4_MicroArch_v1_0.pdf Superscalar implementation of the Simple RISC Processor v1.0]
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# [http://wiki.dcae.pub.ro/images/d/d6/DSD_Project_RISC_FP_Adder_v1_0.pdf Floating-point Execution Unit v.1.0]
  
 
== Assignments ==
 
== Assignments ==
 
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==== First semester ====
 
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model]
 
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model]
 
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor]
 
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor]
 
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)]
 
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)]
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# [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)]
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==== Second semester ====
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# [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)]
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# Floating-point Execution Unit design and verification
  
 
== Resources ==
 
== Resources ==

Versiunea curentă din 12 aprilie 2017 14:23