Diferență între revizuiri ale paginii „Digital Systems Design - Project”

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== Assignments ==
 
== Assignments ==
 
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=== First semester ===
 
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model]
 
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model]
 
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor]
 
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor]
 
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)]
 
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)]
 
# [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)]
 
# [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)]
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=== Second semester ===
 
# [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)]
 
# [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)]
  

Versiunea de la data 23 februarie 2017 16:40