DIC Lab Work 3
Notions and Knowledge Required
- Boolean logic and numbering systems
- Verilog Syntax Verilog_EN
- Using the Altera Quartus II Synthesis Program
- List of pins for DE1 board, List of pins for DE1-SoC board
- Sequential Circuits, The Counter
Example
Describe in Verilog a 32-bit counter with synchronous reset. Link the reset signal to the KEY3 button. Link the less significant 4 bits of the counter's output to the LEDG3 LEDG0 and the LEDs [26:23] on the LEDR3-LEDR0 red LEDs. Observe the variation in speed.
Exercises
Describe in Verilog a circuit that generates a periodic periodic periodic signal using one of the clock signals on the DE1 plate as required by exercises 1-6. This circuit contains a reset counter synchronous and has a number of bits large enough to obtain the desired frequency. Write the Verilog module by following the following requirements:
- The module name must be counter_ks, where k is the period indicated for each exercise
- The module interface must be composed of the following signals:
- clock signal, called clk
- reset signal, called reset
- one bit output signal called out to oscillate with the required period.
The constraints for the reset signal, the LED on which the output and the clock signal are used are specified for each exercise.
For the maximum mark (10), the desired frequency signal will be generated. It will be at most 8 to generate a signal of a frequency as close as possible to this frequency using one of the counter's outputs.
Exercise 1
Output signal has 1s. The clock signal of the CLOCK27 will be used. The reset input is the KEY2 button. The output is connected to LEDR9.
Exercise 2
The output signal has a period of 2 seconds. The clock signal of the CLOCK24 will be used. The reset input is the KEY0 button The output is connected to LEDR5.
Exercise 3
The output signal has a period of 3 seconds. The clock signal of the CLOCK50 will be used. The reset input is the KEY1 button. The output is connected to LEDR0.
Exercise 4
The output signal has a period of 2 seconds. The clock signal of the CLOCK27 will be used. The reset input is the KEY3 button. The output is connected to LEDG7.
Exercise 5
The output signal has a period of 3 seconds. The clock signal of the CLOCK24 will be used. The reset input is the KEY2 button. The output is connected to LEDG0.
Exercise 6
Output signal has 1s. The clock signal of the CLOCK50 will be used. The reset input is the KEY0 button. The output is connected to LEDR4.
Bonus Exercise
Implement the circuit from the previous exercise with a top module that describes structurally the principle of the frequency divider (use a counter and a circuit that resets the counter when the output reaches a certain value). In the top module, the counter and the circuit that generates the reset signal for the counter are instantiated.
Submission of Exercises
For scoring, the following files will be submitted to the e-mail address indicated by the teacher.
An archive zip
- The Verilog file with the .v extension that contains the Verilog description of the circuit. If you have solved the bonus exercise you will send the 3 files.
- A constraint file with the .qsf extension
- A Quartus project file with the .qpf extension
Note that the archive will contain only the 3 files (no directories).
The subject of the email message must be in the [Name] _ [First Name] _ [Group] _Numarator_ [ Exercise] for example Petrica_Lucian_423B_7seg_4
Recommendations for the Teaching Framework
Synchronous circuit concepts (front-end blocks always, non-blocking attributes) will be checked. The idea of the frequency divider will be explained from a clock frequency different from those on the board and the students' questions will be answered.
