Digital Integrated Circuits (lab)

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The Purpose of this Laboratory

The purpose of the Digital Integrated Circuits laboratory is to introduce to students the necessary concepts for the digital design, and assimilation of a new language, Verilog, used for hardware description, as well as the familiarization with some software tools for simulation and synthesis.

Rules and Regulations

The following rules apply to activities in Digital Integrated Circuits laboratory.

  • Laboratory activities are spread in 7 sessions where of 100 minutes each, and will consist in solving of various practical exercises and fulfilling the requirements indicated in laboratory platforms and by the instructor.
  • Students may be absent with the condition of recovering it later on with another group which is approved by an instructor. Any student has the right to do extra work or recover a lab session with another group at any time, but they will not have the priority over the workstations in the laboratory.
  • Only up to 14 students are allowed in laboratory room, where each of them will use a separate computer. Groups shall split in 2 semi-groups. Exceptionally, a student may choose to attend with another group from very beginning, but only if the semi-groups are incomplete.
  • The student evaluation will be made based on resolving the given assignments (50pts) and a lab-exam which will be held on the last laboratory session (50pts). Passive attendance doesn't count as a score.
    • The assignments will be given to students during the laboratory sessions, where each assignment is the evaluation of the related laboratory concepts.
      • The assignments will be fulfilled during the laboratory session and at the end of each laboratory session, fulfilled assignments will be sent to instructor via email.
      • Submitted assignments will be checked automatically against plagiarism and the grades will be graded according to a scale statement that will be sent to students with the assignment.
      • Plagiarism of an assignment will lead to the loss of the whole grade of the related laboratory session.
    • Lab-exam consists of an implementation of a digital circuit, described in Verilog, using the knowledge that is gained during the laboratory sessions.
  • Failing this laboratory automatically leads to repeating it in one of the following academic years. On this subject there are no supplementary exams!
  • Besides the first laboratory session, it is mandatory that students read the laboratory platforms before the lab-session. In the first part of the lab, questions should be asked to clarify things that have not been understood after reading the platform.
  • While leaving laboratory room, do not shut down the computers.
  • Written Verilog models can be transferred at the beginning or at the end of the laboratory using personal email address.
  • Any damages of laboratory platforms, laboratory equipment, connection cables or computers (made intentionally by a student), will be given the grade 4 (Final Grade) for the subject. “ Damages made by the intentions of a student” mean:
    • Touching the metal parts of circuits which are sensitive to electrostatic discharge (MOS);
    • Changing the position of jumpers that will lead to circuit/PCB burn (without adequate understanding of circuit operation)
    • Bending probes and sensors, breaking the cables, or joints and couplings.
    • Damaging the laboratory equipment with improper measurements. (Measuring the voltage with ampere-meter, using the oscilloscope on a maximum sensitivity scale for measuring high voltages, shorting the output of a signal generator, shorting the power supply output, application of improper voltages to the test boards) or by applying improper voltages to the measured circuits;
    • Any physical intervention or rough handling of the case or switches of the panel;
    • Connecting the test boards with other electronic equipments while they are powered on.
  • Instructor will provide the following services for students:
    • Over the first ten minutes of each lab, Instructor will answer the questions of students about the previous labs and the questions regarding current lab materials that must have been read by students at home;
    • All the relevant questions from students about the ongoing laboratory will be answered.
    • In case a student asks a question that shows him/her not being prepared for the ongoing laboratory, then the student will be guided to find the info in the platform and will be politely asked to read the appropriate paragraph.
    • Classes will start at scheduled time, with maximum punctuality.

Tutorials and documentations

  1. Introduction. Verilog_EN syntax
  2. Introduction to FPGA synthesis. Xilinx ISE. Xilinx ISE (13.4) Tutorial
  3. Using the Altera Quartus II Synthesis Program
  4. ROM Memory. IO_Device: The 7 segment display. Sequential_Circuits.The Counter.
  5. RAM_Memory. The Debounce circuit.
  6. The Frequency Divider. The Variable Duty-Cycle Generator. The Decoder.
  7. Automata. PS2 keyboard.

Laboratory works

  1. DIC Lab Work 0
  2. DIC Lab Work 1
  3. DIC Lab Work 2
  4. DIC Lab Work 3
  5. DIC Lab Work 4
  6. DIC Lab Work 5

Installation Tutorial for Xilinx ISE

You may download the installation kit for the last version of Xilinx ISE WebPack from the company’s official Xilinx website. Then select the appropriate version for your operating system. To continue, it is necessary to create an account. The installation kit is compressed into an archive file tar.gz. If you are using the Windows operating system, then you will need a special program to unpack the respective file. 7-zip is one of the options.

You may also download the Xilinx ISE 14.7 from our department’s website: ftp://hermes.arh.pub.ro/public/kits/Xilinx_ISE_DS_14.7_1015_1.tar

Installation on Windows

First of all, download and install the setup kit of 7-zip. Unpack the files into a temporary folder ( you can remove them once installed the program). Then run the executable file setup.exe. In the window that asks you which edition you want to install, select ISE WebPACK. It is the only type of installation that does not require a license. In the window with installation options, select only Use multiple CPU cores for installer archive extraction(if applicable) also Aquire or Manage a License Key. As the last step you must select the destination folder for installation. And finally, remember to delete the temporary folder. After the installation is done, start Xilinx License Configuration Manager. Choose Get Free ISE WebPACK License and follow the instructions.

Installation on Linux

Once the setup kit is downloaded, it should be unpacked in a temporary folder. (So you can remove them once the program is installed). To install the software for all users on a Linux system, you must have rootprivileges. For this open a console and type:

su -

Next you will be asked for the root password. On Ubuntu, where the root has no password set by default, type:

sudo su -

Next you will be asked your user password. We will unpack the kit in the folder /tmp/. To do this, type:

mkdir/tmp/xilinx
cd/tmp/xilinx
tar-xf ~/Downloads/Xilinx_ISE_DS_Lin_13.4_O.87xd.3.0.tar

Let's consider that you have downloaded the setup kit to the folder Downloads from personal Home. If it is elsewhere, or if it has another name, change the path to the archive file.

Now you must run the installer. Type:

cd/tmp/xilinx/Xilinx_ISE_DS_Lin_13.4_O.87xd.3.0/
./xsetup.sh

External Links

  1. https://www.youtube.com/watch?v=lNuPy-r1GuQ - The Binary Logic explained with domino pieces.