Diferență între revizuiri ale paginii „Digital Systems Design - Project”

De la WikiLabs
Jump to navigationJump to search
(Ștergerea conținutului paginii)
 
(Nu s-au afișat 22 de versiuni intermediare efectuate de același utilizator)
Linia 1: Linia 1:
 +
== Design Specifications ==
  
 +
# [http://wiki.dcae.pub.ro/images/e/e6/DSD_Project_RISC_ISA_v2_3.pdf Simple RISC ISA v.2.3]
 +
# [http://wiki.dcae.pub.ro/images/a/a2/DSD_Project_RISC1_MicroArch_v1_0.pdf Pipeline implementation of the Simple RISC Processor v.1.0]
 +
# [http://wiki.dcae.pub.ro/images/0/07/DSD_Project_RISC4_MicroArch_v1_0.pdf Superscalar implementation of the Simple RISC Processor v1.0]
 +
# [http://wiki.dcae.pub.ro/images/d/d6/DSD_Project_RISC_FP_Adder_v1_0.pdf Floating-point Execution Unit v.1.0]
 +
 +
== Assignments ==
 +
==== First semester ====
 +
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model]
 +
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor]
 +
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)]
 +
# [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)]
 +
==== Second semester ====
 +
# [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)]
 +
# Floating-point Execution Unit design and verification
 +
 +
== Resources ==
 +
 +
*[http://www.asic-world.com/verilog/intro.html Introduction to Verilog]
 +
*[http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html Vivado Design Suite Evaluation and WebPACK] (Vivado HL WebPACK is free)
 +
 +
== Announcements ==
 +
 +
[http://www.digilentdesigncontest.com/ Digilent Design Contest 13th Edition]

Versiunea curentă din 12 aprilie 2017 14:23

Design Specifications

  1. Simple RISC ISA v.2.3
  2. Pipeline implementation of the Simple RISC Processor v.1.0
  3. Superscalar implementation of the Simple RISC Processor v1.0
  4. Floating-point Execution Unit v.1.0

Assignments

First semester

  1. Sequential processor golden model
  2. Step by step design of the pipelined Simple RISC Processor
  3. Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)
  4. Step by step design of the superscalar Simple RISC Processor - B (Register renaming)

Second semester

  1. Step by step design of the superscalar Simple RISC Processor - C (Instruction window)
  2. Floating-point Execution Unit design and verification

Resources

Announcements

Digilent Design Contest 13th Edition

Adus de la „http://wiki.dcae.pub.ro/index.php?title=Digital_Systems_Design_-_Project&oldid=5394”