Diferență între revizuiri ale paginii „Digital Integrated Circuits (seminar)”

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Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .
 
Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .
  
* [[CID Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
+
* [[DIC Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
* [[CID Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits
+
* [[DIC Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits
 
* [[DIC Seminar 3]] - Sequential circuits (clock signal, '''always''' and ''' initial ''' vs. '''assign'''
 
* [[DIC Seminar 3]] - Sequential circuits (clock signal, '''always''' and ''' initial ''' vs. '''assign'''
* [[CID Seminar 4]] - Numerals and counting circuits
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* [[DIC Seminar 4]] - Numerals and counting circuits
* [[CID Seminar 5]] - Description of memories in Verilog
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* [[DIC Seminar 5]] - Description of memories in Verilog
* [[CID Seminar 6]] - Finite automata
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* [[DIC Seminar 6]] - Finite automata
  
  
 
You can dowload the programs used on the Altera website:
 
You can dowload the programs used on the Altera website:
 
https://dl.altera.com/13.0sp1/?edition=web
 
https://dl.altera.com/13.0sp1/?edition=web

Versiunea curentă din 27 aprilie 2018 20:00

Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .

  • DIC Seminar 1 - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
  • DIC Seminar 2 - Conditioned instructions, using the 'always' instruction to define combinational circuits
  • DIC Seminar 3 - Sequential circuits (clock signal, always and initial vs. assign
  • DIC Seminar 4 - Numerals and counting circuits
  • DIC Seminar 5 - Description of memories in Verilog
  • DIC Seminar 6 - Finite automata


You can dowload the programs used on the Altera website: https://dl.altera.com/13.0sp1/?edition=web