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- 26 aprilie 2018 16:31 dif ist +1 PC Lab 6
- 26 aprilie 2018 16:31 dif ist +205 PC Lab 6
- 26 aprilie 2018 16:29 dif ist -17 Performance analysis and optimization actuală
- 26 aprilie 2018 16:03 dif ist +7 Using ACS Cluster actuală
- 26 aprilie 2018 16:03 dif ist +23 Using ACS Cluster
- 26 aprilie 2018 16:02 dif ist -9 Using ACS Cluster
- 26 aprilie 2018 15:43 dif ist +736 N Using ACS Cluster Pagină nouă: Steps: 1: copy files on the cluster (scp -r <path to local folder> <moodle id>@fep.grid.pub.ro:~) 2: log in with moodle id (ssh <moodle id>@fep.grid.pub.ro) 3: log in gpu queue (q...
- 26 aprilie 2018 15:33 dif ist +76 PC Lab 6
- 26 aprilie 2018 15:23 dif ist 0 Fișier:VectorAddOpenCL.cpp Cbira a încărcat o nouă versiune pentru Fișier:VectorAddOpenCL.cpp actuală
- 26 aprilie 2018 15:20 dif ist +205 PC Lab 6
- 26 aprilie 2018 15:19 dif ist +335 PC Lab 6
- 26 aprilie 2018 15:16 dif ist +44 PC Lab 6
- 26 aprilie 2018 15:15 dif ist +76 PC Lab 6
- 26 aprilie 2018 15:15 dif ist -10 PC Lab 6
- 26 aprilie 2018 15:14 dif ist +12 PC Lab 6
- 26 aprilie 2018 15:14 dif ist -12 PC Lab 6
- 26 aprilie 2018 15:13 dif ist +39 PC Lab 6
- 26 aprilie 2018 15:12 dif ist +7 PC Lab 6
- 26 aprilie 2018 15:12 dif ist -8 PC Lab 6
- 26 aprilie 2018 15:11 dif ist +8 PC Lab 6
- 26 aprilie 2018 15:11 dif ist 0 N Fișier:VectorAddOpenCL.cpp
- 26 aprilie 2018 15:10 dif ist -3 PC Lab 6
- 26 aprilie 2018 15:10 dif ist +56 PC Lab 6
- 26 aprilie 2018 15:09 dif ist +211 PC Lab 6
- 26 aprilie 2018 14:10 dif ist +264 N PC Lab 6 Pagină nouă: '''Session 6''' '''Task: run matrix-column normalization using OpenCL (https://www.khronos.org/opencl)''' # Install opencl drivers for your platform # Check opencl capable devic...
- 26 aprilie 2018 13:58 dif ist +42 Performance analysis and optimization →Lab sessions
- 26 aprilie 2018 07:27 dif ist +14 CID Seminar 4
- 26 aprilie 2018 07:26 dif ist -1.401 CID Seminar 4
- 26 aprilie 2018 07:20 dif ist +6.657 N DIC Seminar 3 Pagină nouă: In this seminar you will learn what is a secession circuit and how it is described in Verilog. '''Keywords:''clock'',''flip-flop'', blocking''/''non-blocking' Verilog syntax: ''a... actuală
- 26 aprilie 2018 07:20 dif ist -19 Digital Integrated Circuits (seminar)
- 26 aprilie 2018 07:19 dif ist +887 N Digital Integrated Circuits (seminar) Pagină nouă: Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student w...
- 26 aprilie 2018 07:19 dif ist +72 Materiale didactice →Materiale pentru seminar
- 26 aprilie 2018 07:17 dif ist 0 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:17 dif ist -25 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:16 dif ist +131 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:15 dif ist +3 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:15 dif ist +2.363 N IO Device: Segment 7 segment display Pagină nouă: thumb | 7-segment display The 7-segment display is used to display numeric (or even alphanumeric) values in natural format, rather than in binary, using...
- 26 aprilie 2018 07:14 dif ist +23 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:14 dif ist +3 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:12 dif ist -4 DIC Lab Work 4 →Notions and Knowledge Required
- 26 aprilie 2018 07:11 dif ist +39 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 07:11 dif ist +39 DIC Lab Work 4 →Notions and Knowledge Required
- 26 aprilie 2018 07:10 dif ist +39 DIC Lab Work 3 →Notions and Knowledge Required actuală
- 26 aprilie 2018 07:10 dif ist +39 DIC Lab Work 2 →Notions and Knowledge Required
- 26 aprilie 2018 07:10 dif ist +5 DIC Lab Work 1 →Notions and Knowledge Required
- 26 aprilie 2018 07:08 dif ist -16 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 26 aprilie 2018 07:07 dif ist +74 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 26 aprilie 2018 07:06 dif ist 0 DIC Lab Work 1
- 26 aprilie 2018 07:06 dif ist 0 DIC Lab Work 2
- 26 aprilie 2018 07:06 dif ist 0 DIC Lab Work 4 →Notions and Knowledge Required
- 26 aprilie 2018 07:05 dif ist 0 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 07:05 dif ist +110 DIC Lab Work 3
- 26 aprilie 2018 07:04 dif ist -2 Counter actuală
- 26 aprilie 2018 07:03 dif ist -144 DIC Lab Work 4 →Notions and Knowledge Required
- 26 aprilie 2018 07:03 dif ist +257 DIC Lab Work 4 →Notions and Knowledge Required
- 26 aprilie 2018 07:02 dif ist -144 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 07:02 dif ist +246 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 06:59 dif ist 0 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 06:59 dif ist +2 DIC Lab Work 5 →Notions and Knowledge Required
- 26 aprilie 2018 06:59 dif ist +9 DIC Lab Work 5 →Notions and Knowledge Required
- 19 aprilie 2018 16:04 dif ist +38 PC Lab 5 actuală
- 19 aprilie 2018 16:03 dif ist -37 PC Lab 4 actuală
- 19 aprilie 2018 15:19 dif ist 0 PC Lab 5
- 19 aprilie 2018 14:54 dif ist -5 PC Lab 4
- 19 aprilie 2018 14:54 dif ist +5 PC Lab 4
- 19 aprilie 2018 14:54 dif ist -42 PC Lab 4
- 19 aprilie 2018 14:53 dif ist +18 PC Lab 4
- 19 aprilie 2018 14:53 dif ist +61 PC Lab 4
- 19 aprilie 2018 14:52 dif ist +55 N Fișier:Callgrind.out.20485.zip Log report of running compute ASIFT on two adams images actuală
- 19 aprilie 2018 14:34 dif ist 0 PC Lab 4
- 14 aprilie 2018 09:17 dif ist -1 PC Lab 5
- 14 aprilie 2018 09:16 dif ist +14 PC Lab 5
- 14 aprilie 2018 09:12 dif ist +1 PC Lab 5
- 14 aprilie 2018 09:12 dif ist +11 PC Lab 5
- 14 aprilie 2018 09:09 dif ist +6 PC Lab 5
- 14 aprilie 2018 09:09 dif ist +342 PC Lab 5
- 14 aprilie 2018 09:07 dif ist -26 PC Lab 5
- 14 aprilie 2018 09:03 dif ist +718 PC Lab 5
- 14 aprilie 2018 08:58 dif ist +467 PC Lab 5
- 12 aprilie 2018 16:25 dif ist -2 PC Lab 5
- 12 aprilie 2018 16:09 dif ist +3 PC Lab 5
- 12 aprilie 2018 16:08 dif ist -8 PC Lab 5
- 12 aprilie 2018 16:06 dif ist +8 PC Lab 5
- 12 aprilie 2018 16:01 dif ist +3 PC Lab 5
- 12 aprilie 2018 16:01 dif ist +24 PC Lab 5
- 12 aprilie 2018 16:00 dif ist +7 PC Lab 5
- 12 aprilie 2018 16:00 dif ist +43 PC Lab 5
- 12 aprilie 2018 15:57 dif ist +273 PC Lab 5
- 12 aprilie 2018 15:27 dif ist 0 PC Lab 5
- 12 aprilie 2018 15:08 dif ist +127 PC Lab 5
- 12 aprilie 2018 15:03 dif ist 0 PC Lab 5
- 12 aprilie 2018 15:03 dif ist -3 PC Lab 5
- 12 aprilie 2018 15:03 dif ist -6 PC Lab 5
- 12 aprilie 2018 15:02 dif ist +140 PC Lab 5
- 12 aprilie 2018 14:58 dif ist 0 PC Lab 5
- 12 aprilie 2018 14:58 dif ist 0 N Fișier:Hadam.png actuală
- 12 aprilie 2018 14:57 dif ist +461 N PC Lab 5 Pagină nouă: '''Session 5''' Task: run an open-source profiler (valgrind & gperf or visual studio) and improve performance of keypoint extraction in ASIFT C++ code. 1. Download ASIFT project...
- 12 aprilie 2018 14:46 dif ist +59 Performance analysis and optimization →Lab sessions
- 12 aprilie 2018 09:56 dif ist -1 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 12 aprilie 2018 09:54 dif ist -2 Verilog EN →Concatenation operator
- 12 aprilie 2018 09:53 dif ist +23 Verilog EN →Bit access operator
- 12 aprilie 2018 09:45 dif ist 0 Verilog EN →Bitwise logic operators
- 12 aprilie 2018 09:44 dif ist +3 Verilog EN →Bitwise logical operators
- 12 aprilie 2018 09:44 dif ist +5 Verilog EN →Blocks and conditional operators
- 12 aprilie 2018 09:43 dif ist -1 Verilog EN →Blocks and conditional operators
- 12 aprilie 2018 09:42 dif ist +3 Verilog EN →Blocks and conditional operators
- 12 aprilie 2018 09:41 dif ist +1 Verilog EN →Replication operator
- 12 aprilie 2018 09:41 dif ist +1 Verilog EN →Concatenation operator
- 12 aprilie 2018 09:40 dif ist +2 Verilog EN →Bit shift operators
- 12 aprilie 2018 09:39 dif ist +10 Verilog EN →Arithmetic Operators
- 12 aprilie 2018 09:37 dif ist +2 Verilog EN →Clock signal in test modules
- 12 aprilie 2018 09:37 dif ist +1 Verilog EN →Test modules (not synonymous)
- 12 aprilie 2018 09:36 dif ist +29 Verilog EN →Test modules (not synonymous)
- 12 aprilie 2018 09:33 dif ist +2 Verilog EN →Blocks always sequential. Non-blocking assignments
- 12 aprilie 2018 09:32 dif ist +1 Verilog EN →Bit access operator
- 12 aprilie 2018 09:15 dif ist +15.985 Verilog EN
- 12 aprilie 2018 08:54 dif ist 0 RAM Memory actuală
- 12 aprilie 2018 08:52 dif ist -1 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 12 aprilie 2018 08:27 dif ist +2 Verilog EN →Combined always' blocks
- 12 aprilie 2018 08:27 dif ist +7 Verilog EN →Fire (wire) and registers (reg)
- 12 aprilie 2018 08:26 dif ist +4.456 Verilog EN
- 12 aprilie 2018 08:25 dif ist +1 Verilog EN →Verilog Module Interface
- 12 aprilie 2018 08:25 dif ist -563 Verilog EN →Verilog Module Interface
- 12 aprilie 2018 08:23 dif ist +2 Verilog EN →Modules (synthesizable)
- 12 aprilie 2018 08:23 dif ist +2 Verilog EN →Verilog Module Interface
- 12 aprilie 2018 08:22 dif ist -4.438 Verilog EN
- 12 aprilie 2018 08:13 dif ist +5 ROM Memory →Implementing a ROM memory
- 12 aprilie 2018 08:12 dif ist +1 ROM Memory →Interface of a ROM memory
- 12 aprilie 2018 08:12 dif ist +55 ROM Memory →Interface of a ROM memory
- 12 aprilie 2018 08:11 dif ist +5 ROM Memory
- 12 aprilie 2018 08:00 dif ist +40 RAM Memory →Implementing a RAM
- 12 aprilie 2018 07:58 dif ist -2 RAM Memory →Implementing a RAM
- 12 aprilie 2018 07:57 dif ist +2 RAM Memory →Implementing a RAM
- 12 aprilie 2018 07:57 dif ist +3.320 N RAM Memory Pagină nouă: [http://en.wikipedia.org/wiki/Random-access_memory Random Access Memory] are memory circuits. The difference between these and the ROM memories is that RAMs can also write, not jus...
- 12 aprilie 2018 07:56 dif ist +3.003 N DIC Lab Work 5 Pagină nouă: == Notions and Knowledge Required == * Boolean logic and numbering systems * Syntax Verilog * Tutorial_Quartus_II | Using the Al...
- 12 aprilie 2018 07:55 dif ist -1 ROM Memory →Implementing a ROM memory
- 12 aprilie 2018 07:54 dif ist +1 ROM Memory →Implementing a ROM memory
- 12 aprilie 2018 07:54 dif ist -5 ROM Memory →Implementing a ROM memory
- 12 aprilie 2018 07:54 dif ist +4 ROM Memory →Interface of ROM ROM
- 12 aprilie 2018 07:53 dif ist -3 ROM Memory →Interface of ROM ROM
- 12 aprilie 2018 07:53 dif ist +2.107 N ROM Memory Pagină nouă: Most functions implemented by combinational circuits can be described analytically, ie the output can be calculated by applying operators (addition, subtraction, shift, logic o...
- 11 aprilie 2018 23:55 dif ist -1 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 11 aprilie 2018 23:55 dif ist 0 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 11 aprilie 2018 23:55 dif ist +2.670 N The Counter Pagină nouă: The numerator is a sequential circuit that uses a register to generate a sequence of numbers. The simplest numerator generates a sequence of ascending consecutive numbers. The size... actuală
- 11 aprilie 2018 23:55 dif ist +4 DIC Lab Work 3 →Notions and Knowledge Required
- 11 aprilie 2018 23:52 dif ist -2 Counter →Implementing a numerator
- 11 aprilie 2018 23:52 dif ist +3 Counter
- 11 aprilie 2018 23:51 dif ist +4 Counter
- 11 aprilie 2018 23:51 dif ist +1 Counter
- 11 aprilie 2018 23:51 dif ist -3 Counter
- 11 aprilie 2018 23:49 dif ist +2.667 N Counter Pagină nouă: The numerator is a sequential circuit that uses a register to generate a sequence of numbers. The simplest numerator generates a sequence of ascending consecutive numbers. The size...
- 11 aprilie 2018 23:48 dif ist +3 DIC Lab Work 3 →Notions and Knowledge Required
- 11 aprilie 2018 23:46 dif ist -56 DIC Lab Work 4
- 11 aprilie 2018 23:46 dif ist +61 DIC Lab Work 4
- 11 aprilie 2018 23:46 dif ist -3 Sequential Circuits →Clock signal actuală
- 11 aprilie 2018 23:45 dif ist +3 Sequential Circuits →Clock signal
- 11 aprilie 2018 23:45 dif ist 0 DIC Lab Work 4 →Notions and Knowledge Required
- 11 aprilie 2018 23:45 dif ist 0 DIC Lab Work 4 →Notions and Knowledge Required
- 11 aprilie 2018 23:44 dif ist +3 DIC Lab Work 4 →Notions and Knowledge Required
- 11 aprilie 2018 23:44 dif ist -8 DIC Lab Work 4
- 11 aprilie 2018 23:44 dif ist -56 DIC Lab Work 4
- 11 aprilie 2018 23:41 dif ist +2.961 N DIC Lab Work 4 Pagină nouă: == Notions and Knowledge Required == * Boolean logic and numbering systems * Syntax Verilog * Tutorial_Quartus_II | Using the Al...
- 11 aprilie 2018 23:39 dif ist +1 Verilog EN →Blocks assign
- 11 aprilie 2018 23:38 dif ist +4 Verilog EN
- 11 aprilie 2018 23:37 dif ist -114 Verilog EN
- 11 aprilie 2018 23:35 dif ist +5 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 11 aprilie 2018 23:27 dif ist -22 Sequential Circuits →Memory Circuits. Register
- 11 aprilie 2018 23:21 dif ist -3 Sequential Circuits →Memory Circuits. Register
- 11 aprilie 2018 23:21 dif ist +81 Sequential Circuits →Memory Circuits. Register
- 11 aprilie 2018 23:16 dif ist +2 Sequential Circuits →Memory Circuits. Register
- 11 aprilie 2018 23:15 dif ist +2.730 N Sequential Circuits Pagină nouă: Sequential circuits are circuits that are synchronized by a clock signal, ie whose outputs change only on the positive (or negative, clockwise) front of the clock. == Clock signal...
- 11 aprilie 2018 23:13 dif ist 0 DIC Lab Work 3
- 11 aprilie 2018 22:57 dif ist -3 DIC Lab Work 3 →Exercises
- 11 aprilie 2018 22:57 dif ist +10 DIC Lab Work 3 →Exercises
- 11 aprilie 2018 22:55 dif ist +4.118 N DIC Lab Work 3 Pagină nouă: == Notions and Knowledge Required == * Boolean logic and numbering systems * Syntax Verilog * Tutorial_Quartus_II | Using the Al...
- 11 aprilie 2018 22:53 dif ist +2 DIC Lab Work 2 →Exercise 5
- 11 aprilie 2018 22:51 dif ist +1 DIC Lab Work 2 →Exercise 2
- 11 aprilie 2018 22:50 dif ist +1 DIC Lab Work 2 →Submission of Exercises
- 11 aprilie 2018 22:50 dif ist -21 DIC Lab Work 2
- 11 aprilie 2018 22:49 dif ist +12.607 N DIC Lab Work 2 Pagină nouă: == Notions and Knowledge Required == * Using the Altera Quartus II Synthesis Program * [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_d...
- 11 aprilie 2018 22:35 dif ist +1 Quartus II tutorial →2. Source file design (top-level design entity) actuală
- 11 aprilie 2018 22:34 dif ist +9 Quartus II tutorial
- 11 aprilie 2018 22:31 dif ist 0 Quartus II tutorial →3. compiling
- 11 aprilie 2018 22:30 dif ist -1 Quartus II tutorial
- 11 aprilie 2018 22:30 dif ist -1 Quartus II tutorial
- 11 aprilie 2018 22:23 dif ist 0 Quartus II tutorial →3. compiling
- 11 aprilie 2018 22:22 dif ist -3 Quartus II tutorial →3. compiling
- 11 aprilie 2018 22:21 dif ist +7.650 N Quartus II tutorial Pagină nouă: '''Programming the experimental board DE1 with Quartus II (version 13.0sp1) Example: synthesis of a 4-bit sumer. ''' To open the Quartus II application you can use: - the shortc...
- 11 aprilie 2018 22:19 dif ist 0 DIC Lab Work 1 →Recommendations for Teachers
- 11 aprilie 2018 22:17 dif ist +1 DIC Lab Work 1 →Example
- 11 aprilie 2018 22:17 dif ist +4.247 N DIC Lab Work 1 Pagină nouă: == Notions and Knowledge Required == * Using the Altera Quartus II Synthesis Program * [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_d...
- 11 aprilie 2018 21:26 dif ist -10 Introduction. Verilog HDL (Verilog syntax) →Computation and control
- 11 aprilie 2018 21:18 dif ist +48 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:17 dif ist -12 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:16 dif ist +42 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:14 dif ist -42 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:14 dif ist 0 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:13 dif ist -31 DIC Lab Work 0 →Notions and Knowledge Required
- 11 aprilie 2018 21:09 dif ist 0 DIC Lab Work 0 →Example
- 11 aprilie 2018 21:08 dif ist +2.847 N DIC Lab Work 0 Pagină nouă: == Notions and Knowledge Required == * Boolean Logic and Numerical Systems == Development board ==...
- 11 aprilie 2018 21:06 dif ist -24 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:58 dif ist -98 Introduction. Verilog HDL (Verilog syntax) →Circuits
- 11 aprilie 2018 20:53 dif ist 0 Introduction. Verilog HDL (Verilog syntax) →Circuits
- 11 aprilie 2018 20:52 dif ist 0 Introduction. Verilog HDL (Verilog syntax) →Computation and control
- 11 aprilie 2018 20:51 dif ist 0 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:50 dif ist -5 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:48 dif ist -67 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:46 dif ist -12 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:44 dif ist -324 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:41 dif ist -195 Introduction. Verilog HDL (Verilog syntax)
- 11 aprilie 2018 20:13 dif ist -150 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 5 aprilie 2018 08:22 dif ist +1.954 CID Seminar EN actuală
- 5 aprilie 2018 08:21 dif ist +15 CID Seminar EN →Exercise 2
- 5 aprilie 2018 08:20 dif ist -1 CID Seminar EN →Exercise 2
- 5 aprilie 2018 08:20 dif ist -9 CID Seminar EN
- 5 aprilie 2018 08:19 dif ist +4.698 N CID Seminar EN Pagină nouă: In this seminar you will learn what is a secession circuit and how it is described in Verilog. '''Keywords:''clock'',''flip-flop'', blocking''/''non-blocking' Verilog syntax: ''a...
- 5 aprilie 2018 08:16 dif ist +1 Circuite integrate digitale (seminar)
- 5 aprilie 2018 08:16 dif ist +18 Circuite integrate digitale (seminar)
- 29 martie 2018 13:25 dif ist 0 PC Lab 4
- 29 martie 2018 13:25 dif ist 0 N Fișier:Lnorm.png actuală
- 29 martie 2018 13:25 dif ist +570 N PC Lab 4 Pagină nouă: '''Session 4''' Speed optimization over i5/i7 x64 arch: Compute distance between two vectors of points in 128-D space (128 coordinates). The purpose is to find the maximum dista...
- 29 martie 2018 12:35 dif ist +32 Performance analysis and optimization →Lab sessions
- 29 martie 2018 09:30 dif ist -3 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:28 dif ist -23 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:21 dif ist +21 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:17 dif ist -4 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:08 dif ist -1 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:07 dif ist -5 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:06 dif ist -28 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 09:05 dif ist -12 Verilog EN →Wires (wire) and registers (reg)
- 29 martie 2018 08:57 dif ist +4.505 Verilog EN →Fire (wire) and registers (reg)
- 29 martie 2018 08:55 dif ist 0 Verilog EN →Verilog Module Interface
- 29 martie 2018 08:55 dif ist -9 Verilog EN
- 29 martie 2018 08:54 dif ist +1 Verilog EN →Verilog Module Interface
- 29 martie 2018 08:53 dif ist -1 Verilog EN →Verilog Module Interface
- 29 martie 2018 08:50 dif ist +4.562 N Verilog EN Pagină nouă: == Modules (synthesizable) == The Verilog language is structured on modules. Each module represents a circuit that implements a certain function. For example, a module may be a su...
- 29 martie 2018 08:50 dif ist +2 DIC Seminar 1 →Notions and Knowledge Required
- 29 martie 2018 08:49 dif ist +1 DIC Seminar 1
- 29 martie 2018 08:37 dif ist -1 DIC Seminar 1 →Exercise 3
- 29 martie 2018 08:37 dif ist -22 DIC Seminar 1
- 29 martie 2018 08:34 dif ist -1 DIC Seminar 1
- 29 martie 2018 08:34 dif ist -11 DIC Seminar 1
- 29 martie 2018 08:32 dif ist +2.946 DIC Seminar 1
- 29 martie 2018 08:29 dif ist +4.782 N DIC Seminar 1 Pagină nouă: In this seminar you will learn to describe some simple digital circuits in Verilog language and use the Quartus II and ModelSim programs. '' 'Keywords:' '' logical gates, ports,...
- 29 martie 2018 08:28 dif ist +885 N Digital Integrated Circuits (sem) Pagină nouă: Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student w... actuală
- 29 martie 2018 08:25 dif ist +91 Main Page
- 29 martie 2018 07:53 dif ist +150 Digital Integrated Circuits (old lab) →Tutorials and documentations
- 29 martie 2018 07:51 dif ist 0 Verilog →Module (sintetizabile)
- 22 martie 2018 19:04 dif ist +20 Introduction. Verilog HDL (Verilog syntax) →Verilog HDL
- 22 martie 2018 18:43 dif ist -194 Introduction. Verilog HDL (Verilog syntax) →Circuits