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* [https://users.dcae.pub.ro/~zhascsi/courses/add/add3.pdf Carry Lookahead Adder - iterative design] | * [https://users.dcae.pub.ro/~zhascsi/courses/add/add3.pdf Carry Lookahead Adder - iterative design] | ||
* [https://users.dcae.pub.ro/~zhascsi/courses/add/add4.pdf Carry Lookahead Adder - recursive design] | * [https://users.dcae.pub.ro/~zhascsi/courses/add/add4.pdf Carry Lookahead Adder - recursive design] | ||
| + | |||
| + | == Test code for adder == | ||
| + | <syntaxhighlight lang="SystemVerilog"> | ||
| + | module test; | ||
| + | |||
| + | logic [31:0] a; | ||
| + | logic [31:0] b; | ||
| + | logic [32:0] s; | ||
| + | |||
| + | cla #(32) dut (.a(a), .b(b), .s(s)); | ||
| + | |||
| + | initial begin | ||
| + | repeat(100) begin | ||
| + | #1 | ||
| + | a = $random; | ||
| + | b = $random; | ||
| + | #1 | ||
| + | if(s !== a + b) | ||
| + | $display("ERROR\n"); | ||
| + | else | ||
| + | $display("OK\n"); | ||
| + | end | ||
| + | end | ||
| + | |||
| + | endmodule | ||
| + | </syntaxhighlight> | ||
== Projects == | == Projects == | ||
Versiunea curentă din 28 mai 2025 15:13
- Structured design with verilog
- Carry Lookahead Adder - iterative design
- Carry Lookahead Adder - recursive design
Test code for adder
module test;
logic [31:0] a;
logic [31:0] b;
logic [32:0] s;
cla #(32) dut (.a(a), .b(b), .s(s));
initial begin
repeat(100) begin
#1
a = $random;
b = $random;
#1
if(s !== a + b)
$display("ERROR\n");
else
$display("OK\n");
end
end
endmodule
